library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 

entity BCD10 is
    port (
        CLK: in std_logic;
        EN: in std_logic;
        CLR: in std_logic;
        BCD: out std_logic_vector(3 downto 0);
        CO: out std_logic
    );
end BCD10; 

architecture rtl of BCD10 is
    signal cnt: std_logic_vector(3 downto 0):="0000";
begin
    process(CLK,CLR)
    begin
        if CLR='0' then
            cnt<="0000";
        elsif CLK'event and CLK='1' and EN='1' then
            if cnt="1001" then cnt<="0000";
            else cnt<=cnt+'1'; 
            end if;
        end if;
    end process;
    BCD<=cnt;
    CO<= '1' when cnt="1001" else '0';
end rtl;